Reliable BMS Boards Start With Quality PCB Manufacturing

A BMS board carries the full pack current through the same copper that its protection chip reads in millivolts. That double duty separates it from an ordinary power board. It is also why fabrication quality shows up directly in how well the battery is protected. The protection IC never measures current directly. It reads a small voltage across a sense resistor or across the MOSFETs and trips when that voltage crosses a threshold, such as 150 mV.

Figure 1: A multi-cell BMS board with heavy copper power paths

This guide shows you what a BMS board is, how to size its power paths, and how to route its sensing. It goes on to discuss manufacturing constraints for the design and inspection to ensure each board in a batch is like the prototype that passed inspection.

Understanding the BMS Board

A BMS board measures and can switch off. The jobs produce the copper that you draw later; the functions are first, and the layout follows.

What Is a BMS Board?

There is a BMS (battery management system) board located between the battery cells and the load. It prevents any cell from going outside of its safe operating window.

For instance, this can be two chips on a single 18650 cell, a DW01A protection IC, and a dual MOSFET, FS8205A. It expands to a monitor IC (e.g., TI BQ76952) and a microcontroller on a 16-series pack.

Figure 2: Block diagram of a BMS board showing measurement, decision, and switching sections

All versions have 3 building blocks: A measurement section is provided for reading the cell voltages, pack current, and temperature. Those readings are compared to limits in a decision section, and a switching section, typically two N-channel MOSFETs in series, opens the path. Smart battery BMS board: A communication port, such as I2C, CAN, or UART, is added. It also tracks the state of charge, allowing the pack to report to a charger or host. That does not change the fact that the incumbent copper must be carried; however, it does introduce digital routing.

Key Functions of a BMS Board

A BMS board has 5 functions, and each function measures a different variable, each placing a different strain on the capability of the board:

• Overcharge Protection: prevents overcharging if any battery is over the top-end voltage.
• Over-discharge protection: prevents discharge in the event of a cell dropping below its lower end of the discharge range.
• Overcurrent and short-circuit protection: disconnects the circuit if the current exceeds a predefined limit.
• Temperature protection: prevents charging or discharging when outside the safe temperature range.
• Cell balancing: balances cell voltages to prevent a single cell from limiting pack voltage.

Designing a BMS Board for Electrical Performance

BMS board design is a compromise between the ability to handle tens of amps and the need to maintain clean millivolt readings. Each of copper weight, placement, and stackup attends to part of that trade.

Power Paths, Trace Width, and Copper Thickness

Each milliohm in the power path from the pack terminal through the MOSFETs and shunt is a source of heat. A 1 oz (35 µm) copper layer measures about 0.5 mΩ per square, so a trace 10 mm (394 mil) wide and 50 mm (1,969 mil) long comes to roughly 2.5 mΩ. That trace burns off around 1W at 20A.

Figure 3: Trace width versus current for 1 oz and 2 oz outer copper at a 10 °C rise

The trace widths derived from the legacy IPC-2221 empirical relationship are based on the following equation for outer-layer copper:

I = 0.048 × ΔT⁰·⁴⁴ × A⁰·⁷²⁵

Where:

• I = Current through the trace (A)
• ΔT = Allowable trace temperature rise above ambient (°C)
• A = Copper trace cross-sectional area (mil²), calculated as trace width × copper thickness

For the trace-width estimates discussed here, the assumed temperature rise is ΔT = 10 °C, and the coefficient 0.048 applies to external (outer-layer) copper. IPC-2221B dropped that chart, and current capacity now sits in IPC-2152, which IPC lists as no longer maintained. The old chart oversizes conductors, so treat the table as a conservative start; its inner-layer curve gives about 2.6 times the width.

Width grows faster than current here; doubling the copper weight halves the width at the same current. Above about 10 A, the path becomes a copper pour on both layers. Vias stitch those pours together, so the two layers share the current.

Component Placement and Thermal Management

Placement begins with the power path as the MOSFETs and shunt carry the total pack current. They should be arranged in a straight line, between the input and output pads, as each deviation from the straight line introduces resistance. Two MOSFETs (2 mΩ) dissipating 3.6 W at 30 A require generous copper drain tabs. The thermal conductivity of FR-4 is about 0.3 W/mK, so only copper plating on thermal vias can help to conduct heat to the other side.

Figure 4: Thermal zoning on a BMS board with the power path

As a rule, 0.3 mm (12 mil) vias on a 1.0 to 1.2 mm (40 to 47 mil) pitch under each MOSFET pad are a good starting point. The thermistor must be mounted where the heat it would sense starts: against a cell or near the MOSFETs. The monitor IC should be placed on the quiet side of the board (opposite the switching path). Avoid placing both near the balancing resistors, as the resistors' heat will cause the sensor to show a warmer pack than it actually is.

Layer Stackup, Grounding, and Signal Routing

A single-cell protection board can be used on two layers, while a multi-cell board with a BQ76952-class monitor can use four. When using this particular stackup, parts are on top, followed by power copper, and then solid ground on layer two. The cell taps and sense lines are on layer 3 with power on the bottom. The inner ground provides each sense line with a short return path, so the ADC will not see switching noise.

Figure 5: Kelvin sense connection from a shunt resistor

Grounding is done in two zones connected at a common point. The power ground supplies the pack current, and the measurement ground serves as a reference for the monitor IC. They meet once outside the sense resistor; therefore, the load current does not pass through the reference copper. If it did, all the cell voltages measured would change. The sense lines from the shunt should be Kelvin connections (a pair of traces from the inside of the shunt pads, not from the power copper surrounding the shunt pads). Take that pair together and close it through the RC filter to the IC. Both lines then pick up the same interference, which is canceled by the differential input.

Preparing BMS Board Designs for Manufacturing

Even a BMS board running in simulation mode will still hit a fabricator's drilling, plating, and etching limits. When designing, use the recommended value rather than the minimum to maintain batch consistency.

Via, Pad, and Feature Size Requirements

The number of vias in a BMS power path is more important than the size of the vias. A 0.3 mm (12 mil) via barrel unrolls into a copper strip about 0.94 mm (37 mil) wide. That strip is plated at ~18 µm and will rate slightly more than 1 A per 10 °C increase, so plan one via per amp when stitching pours.

DFM and Manufacturing Tolerances

DFM (Design for Manufacture) is the ability to draw features that a fabricator can repeat on every panel. It's the biggest problem with BMS boards, as the etching of the thick copper goes sideways along with it going down. Such a sense trace can thus look thinner on a 2oz layer.

Tolerances are important anywhere along the board where it interfaces with a mechanical part. Plated holes at JLCPCB hold +0.13/-0.08 mm (+5/-3 mil), so a 2.0 mm (79 mil) terminal pin needs a hole near 2.2 mm (87 mil). For boards 1.0 mm or thicker, a ±10% thickness deviation can be important when sliding into a board holder .

Complete these checks before ordering:

• Make sure the fabricator's rules are loaded in DRC rather than the tool defaults.
• Make sure each power pour includes the via count and the via's current requirements.
• Check that the sense traces leave the shunt from the inner pad edges.
• Check cell tap spacing for electrical voltage between adjacent traces.
• Use a Gerber/drill file viewer prior to uploading.

The PCB Design Rules Guide provides an overview of the general DRC setup. 2-4 are additional components on a board for a BMS, since a standard DRC can't distinguish between a power pour and a signal net.

Material and Surface Finish Selection

The standard FR-4 is adequate for most BMS boards, and the important property is Tg, the temperature at which the resin softens. JLCPCB's default is TG135-140; you can also choose TG155 or TG170. If the area around the MOSFET gets too hot or if it short-circuits repeatedly, a higher Tg will cause plated holes to extend less during each cycle .

The flatness of the pads is determined by surface finish. The cheap and strong HASL for a DW01A is lead-free, but the solder thickness varies. ENIG (under thin gold) is a nickel-based surface that does not develop uneven surfaces, which is helpful for a fine-pitch monitor IC and wide MOSFET pads. Although also flat, OSP's short shelf life makes it an appropriate product for boards assembled shortly after delivery.

Manufacturing BMS Boards for Consistent Quality

Consistency is not only a design property but also a fabrication property. The only way to get matching boards is to remain within limits during etching, drilling, plating, and inspection using the same Gerber files.

Fabrication Accuracy and Process Control

The etching process determines the width of each trace, and on a BMS board, the width is also a measure of resistance. The etchant will eat away the copper side-to-side and down, so fabricators make the artwork slightly wider than the desired trace. When that compensation varies, the shunt connection's resistance varies from batch to batch.

Process control involves making measurements rather than relying on the machine's settings. Inner layers are examined optically after etching, prior to lamination, obscuring them. After pattern plating, AOI catches an open or narrowed trace (before the panel is scrapped). A multilayer board is also subject to the lamination risk when heavy copper is used. The inner copper is thick, and deep gaps will form between features that will need to be filled with prepreg resin during the pressing process. Otherwise, gaps are created between layers. Inner copper is as thick as 2 oz at JLCPCB, and outer copper can be as thick as 4.5 oz in 2-layer boards.

Drilling, Plating, and Dimensional Control

Vias, which are formed by drilling and plating, determine the distribution of current from power pour to power pour and hence the even spread. The holes are within approximately 3/4 mil (+/- 0.075 mm) of their drawn position. This is why the 0.25 mm (10 mil) annular ring is important; it allows for that offset without breaking out.

Then, plating is performed to deposit copper on the hole wall, with a standard thickness of 18 µm. IPC-6012F Class 3 requires an average of 25 µm (1 mil), so if a board is Class 3, it should state so. For ordinary builds, it is more economical to ask for vias, since this reduces current costs, and adding thicker barrels is just as expensive as adding vias.

Dimensional control is ±0.2 mm (8 mil) for outline in CNC routing and ±0.4 mm (16 mil) for V-cut edges. If your board is intended to mount in a slot in an enclosure, a BMS board is better routed than scored, and the V-cut panelization standards indicate where scoring is OK.

Inspection and Quality Verification

Inspection is carried out in 2 stages: the bare board and the assembled board fail in different ways. The bare board is inspected for conformance to IPC-A-600M and tested for opens and shorts against the netlist. JLCPCB here employs flying-probe testing and does not need to make a custom fixture for a prototype run.

Functional testing is the final test, since a board can pass all the other tests and still trip at the wrong current. Each cell is replaced by a programmable source, called a cell simulator, that pushes the board to each trip point, and a tester documents each trip point. If a threshold has shifted since the prototype, there is likely copper in the sense loop.

FAQs About BMS Boards

Conclusion

Selecting the appropriate protection IC is not the only factor in ensuring a reliable BMS board. The PCB layout influences the accuracy and safety of the system's operation. Proper Kelvin connections and careful grounding assist the IC in accurately measuring current, and the thickness of the copper and the width of the trace contribute to heat generation in high-current paths. Firm PCB production is equally crucial, particularly when producing hundreds or thousands of boards that must function in the same way.

More cells and higher currents of battery packs make accurate sensing and reliable protection more critical. Minor layout variations and manufacturing tolerances may influence the timing of protection circuit responses. When your design is complete, JLCPCB can provide 2 oz copper, ENIG surface finish, and flying-probe testing to ensure your BMS boards meet the design requirements.