Optimizing High-Voltage Circuit Safety with PCB Dielectric Strength

Dielectric strength is the number engineers quote to prove a board is safe at mains voltage. It is also the number most often used wrongly. A laminate datasheet lists dielectric strength in kilovolts per millimeter. With a 1.6 mm (63 mil) board, it is tempting to simply multiply the value by the board thickness.

Figure 1: PCB showing an isolation slot milled between primary and secondary copper

And the same arithmetic fails, because breakdown never averages across a material. It hunts for the weakest path through it, and a thicker slab holds more resin, more glass bundles, and more voids along the way. Once kV/mm stops being a multiplier, high-voltage work becomes a spacing and materials problem again. This guide covers how dielectric strength is measured and how it differs from dielectric constant. It then compares FR-4, high-Tg, and ceramic substrates, and turns clearance and creepage rules into millimeters on your layout.

Fundamentals of PCB Dielectric Strength and Insulation

Insulation on a printed board is judged by two numbers that sound alike. They answer different questions, because one belongs to the material and the other belongs to the object you built from it.

What is Dielectric Strength and How Is It Measured?

Dielectric strength is the maximum electric field an insulator holds before it starts conducting. It is a field rather than a voltage, so it carries units of kV/mm or V/mil.

Figure 2: Dielectric strength falling as sample thickness rises

Laminate suppliers measure it two different ways, and confusing them is the most common error in material selection.

• Electric Strength — IPC-TM-650 2.5.6.2: Measures breakdown perpendicular to the laminate layers, through the board thickness. The result is reported as an electric field, usually in kV/mm. IPC-4101 sheets often specify a minimum of 30 kV/mm.
• Dielectric Breakdown — IPC-TM-650 2.5.6: Measures failure parallel to the laminate layers, along the glass and resin. The result is reported as a single voltage in kV. For example, Kingboard KB-6165F lists 65 kV for this test, but that value should not be applied directly to a thin prepreg layer.

Measured values generally decrease as the specimen thickens, even when the material is identical.

Thickness buys real withstand voltage, but it buys progressively less of it. So a kV/mm figure measured on one sample cannot be scaled to a different geometry.

PCB Dielectric Strength vs. PCB Dielectric Constant

The PCB dielectric constant, denoted as Dk, measures how much charge a material stores per unit voltage. It has nothing to do with insulation safety. Dk sets how fast a signal travels and what impedance a trace presents, which is why it lives in the signal-integrity half of a datasheet. These properties describe different behaviors, so they are measured differently and should not be treated as interchangeable.

• Permittivity (Dk) and loss tangent (Df): Measured using IPC-TM-650 2.5.5 methods. A small AC field is applied, and the material’s electrical response is measured without destroying the sample.
• Electric strength: Measured using IPC-TM-650 2.5.6.2. The voltage is increased until the laminate breaks down, so the test is destructive.

Loss tangent, or Df, tells you how much electrical energy is converted into heat. It is therefore mainly a signal-loss parameter, not an insulation-safety value. Standard FR-4 may have a Dk around 4.4 at 1 GHz, but neither Dk nor Df tells you whether a high-voltage gap will arc.

Higher Dk can even make high-voltage behavior slightly worse by concentrating electric fields around sharp copper edges. The effect is usually much smaller than spacing and geometry, but it is still worth understanding.

Key Factors Influencing PCB Dielectric Materials

Material choice for a high-voltage board is rarely won on kV/mm alone. The substrate with the highest field strength is often the wrong one, because thermal survival and surface tracking usually decide the outcome.

Comparative Analysis of Common PCB Substrates (FR-4, High-Tg, Ceramic)

Standard FR-4 covers most mains-voltage work, and it does so honestly. Woven glass in an epoxy matrix yields a through-thickness field strength of approximately 30-40 kV/mm.

Ceramic is where the intuition breaks most sharply. A 96% alumina substrate, such as CoorsTek AD-96, sits near 8.3 kV/mm, which is well below plain FR-4. It is still the material of choice in demanding power modules, because it wins on thermal conductivity, dimensional stability, and the fact that inorganic ceramics do not carbon-track at all.

Impact of Operating Temperature, Moisture, and Layer Thickness

Temperature attacks insulation through the resin rather than the glass. Once the board runs near its glass transition temperature, the epoxy softens, and insulation resistance falls with it. Keeping the continuous operating temperature 20 to 30 °C below Tg is the practical guard band, which is why selecting the Tg of your PCB belongs early in a high-voltage project.

Figure 3: Field strength, Dk, and tracking behavior compared

• Moisture is the quieter problem: FR-4 absorbs only about 0.1-0.2% of its weight in water. That water sits in the resin, and along the glass interfaces where the field is strongest, and published work puts the resulting loss of dielectric strength as high as 20%. So a board qualified in a dry lab can behave differently inside a humid pump housing.
• Layer thickness matters in a way the datasheet hides: Your real insulation between two inner-layer nets is one or two prepreg plies, often 0.1 mm (4 mil) rather than the full board. A resin-poor style, such as 7628, fills differently from a thin 1080 ply, so the pressed result varies with the copper above and below it.

Testing and Qualification of PCB Insulation Performance

Testing insulation splits into two jobs that get confused constantly. One measures a material property in a laboratory, while the other proves that a finished assembly survives a defined stress.

Executing a Standardized Dielectric Strength Test (Hi-Pot Testing)

A hi-pot test, short for high potential, is a dielectric withstand test rather than a measurement. You apply a defined voltage across an isolation barrier for a defined time and watch the leakage current. The answer is a pass or a fail, so it never produces a kV/mm figure and was never meant to.

The actual test voltage comes from the applicable safety standard, but a common rule for mains equipment is 2× the working voltage + 1000 V AC. Qualification testing typically applies that voltage for 60 seconds. Production testing often uses a shorter test to avoid repeatedly stressing otherwise good insulation.

The basic test sequence is the same for a bare PCB or a finished assembly.

1. Identify the barrier under test and short every net on each side together, so the tester sees two nodes rather than a hundred.
2. Set the leakage trip threshold before applying voltage, typically a few milliamps, once the Y-capacitors are removed.
3. Ramp the voltage rather than switching it on, since a hard step delivers a capacitive surge that trips a healthy board.
4. Hold at the target voltage for the specified dwell, watching for leakage that climbs rather than settling.
5. Ramp back down and confirm the barrier is discharged, because a 1.6 mm (63 mil) board is still a capacitor.

Identifying Insulation Breakdown and Creepage Risks

Insulation fails along three separate paths, each with its own rule. Puncture goes straight through the dielectric, which is what dielectric strength describes. Flashover jumps through the air and is governed by clearance, while tracking crawls across the surface and is governed by creepage.

Figure 4: A hi-pot tester performing a dielectric withstand test on a mains-input PCB

The comparative tracking index (CTI) measures how well an insulating material resists surface tracking, using the IEC 60112 test. IEC 60664-1 then places materials into four groups based on their CTI value. That material group is used to determine the required creepage distance for the insulation system.

• Group I, CTI of 600 V and above, allows the shortest creepage distances for a given working voltage.
• Group II, CTI from 400 V up to 600 V, sits between the extremes and covers many upgraded laminates.
• Group IIIa, CTI from 175 V up to 400 V, is where ordinary FR-4 lands, so it is your default unless you specify otherwise.
• Group III b, CTI from 100 V up to 175 V, also applies whenever a material has no declared CTI at all.

Flux residue and dust accelerate all of it, which is what the pollution degree exists to capture, so choosing the right CTI value matters as much as choosing a thickness.

Engineering Strategies for High-Voltage PCB Layouts

All of this becomes useful only when it turns into millimeters in your design rules. Two standards do that job; they answer different questions, and a safe layout satisfies both.

Clearance and Creepage Distance Optimization Rules

Clearance is the shortest distance through air between two conductors. Creepage is the shortest distance along the surface of the insulation between the same two conductors. They are set by different physics, so they take different inputs.

Clearance is dimensioned against a short transient, whereas creepage is dimensioned against the working voltage that sits there for years. So clearance depends on rated impulse voltage, pollution degree, and altitude, while creepage depends on RMS working voltage, pollution degree, and material group. Creepage must never be smaller than clearance, so on a compact board, the creepage rule usually determines the gap. The table below carries the three columns you will actually use, and treating PCB voltage clearance as a per-layer rule is what makes it workable.

Inner-Layer Isolation Protocols in Multi-Layer Boards

Inner layers are governed by dielectric spacing rather than creepage. There is no air path and no contamination between the two buried layers. A typical four-layer stackup leaves roughly 0.1 mm (4 mil) of prepreg between an outer layer and the adjacent plane.

Figure 5: Clearance, creepage, and the effect of a milled isolation slot

For example, a 400 V potential across that gap produces a field near 4 kV/mm, which is comfortable for FR-4 but far tighter than the board thickness suggests. Two prepreg plies instead of one is the standard defense, because a single ply can develop a resin-starved region over dense copper.

Copper on every layer has to respect the same barrier, and this is the mistake that survives review most often. A ground plane poured to the board edge quietly bridges an isolation gap you drew carefully on the top layer. So the keepout has to be cut through all layers, including planes, thermal reliefs, and any stitching vias near the boundary.

JLCPCB's Advanced Material Selection & Quality Testing Standards

A manufacturer contributes two things to insulation performance. One is the laminate that presses into your board, and the other is the evidence it can hand you about that laminate.

High-Quality Insulating Laminates and Rigorous Material Traceability

JLCPCB builds standard FR-4 orders on Grade A laminates from Nan Ya, Kingboard, and Shengyi. It publishes the actual datasheets rather than describing them generically, so you can read the numbers yourself. The JLCPCB certifications page carries sheets for Nan Ya NP-140F and NP-155F, Kingboard KB-6164 and KB-6165F, and Shengyi S1141, S1000H, and S1000-2M at Tg 170.

That matters because those sheets contain what a safety file needs. KB-6165F is a mid-Tg grade at 150 °C, with a comparative tracking index above 175 V and a dielectric breakdown of 65 kV on the parallel test. Writing that grade into your fabrication notes is meaningfully different from writing FR-4 and hoping.

Comprehensive High-Voltage Insulation and Dielectric Testing

Every bare board is electrically tested before it ships, using a flying probe for prototypes and a fixture for volume runs. That test drives every net against the netlist and checks continuity and isolation. It is not a hi-pot test, and treating it as one would be a mistake. Bare-board electrical test confirms that the two nets are separate at low voltage. A dielectric withstand test confirms that the separation holds at several kilovolts, which is a different question, and JLCPCB does not publish that as a service on customer boards.

Figure 6: Showing where fab testing ends and compliance testing begins

So the routine hi-pot on your finished assembly belongs to you or to a compliance test house. The design work described earlier is what makes it pass. The rest is a design decision you can make today. Set your clearance rules per layer, draw the isolation barrier across the whole stackup, name the laminate grade in your notes, then upload your high-voltage design and read the DFM report before you commit to a build.

FAQs about PCB Dielectric Strength

Conclusion

Dielectric strength earns its reputation as a safety number only when you read it as a material property. The laminate tells you how hard the resin resists a field, while the geometry decides what field it will actually see. Those two only meet through the spacing tables, which is why a 1.6 mm board and a 0.1 mm prepreg ply can share a datasheet and behave nothing alike.

The habits that follow are cheap to adopt. Separate clearance from creepage in your design rules, and name the laminate grade instead of writing FR-4. Treat the solder mask as manufacturing protection rather than safety insulation, and keep the operating temperature well below Tg. JLCPCB's published laminate datasheets and DFM checks make the material half straightforward, so your attention can go to the spacing.