Getting PCB Characteristic Impedance Right for Reliable Signals

Characteristic impedance decides whether a fast edge reaches its receiver cleanly, yet a multimeter cannot measure it. A 50 Ω trace reads a small fraction of an ohm from end to end. The meter sees copper resistance, while the signal sees something else entirely. A rising edge never sees the whole trace at once. It sees only the stretch of copper it has reached so far. To move forward, it must charge the plane beneath it and build a magnetic field around the trace.

Figure 1: A controlled impedance trace and its reference plane on a multilayer PCB

That ratio between the two sets is what determines how much current the edge draws per volt. This guide discusses the nature of characteristic impedance on a PCB and what quantities determine it. It then explores how fabricators acquire and validate that value and which interfaces are truly value-laden. The result is a stackup that reaches the desired number without repeating.

What Is Characteristic Impedance in a PCB?

Characteristic impedance is not the copper's; it is the trace's and its reference plane. Hence, it can be worked out from geometry, and a gap in the plane spoils it.

How Characteristic Impedance Works in Transmission Lines

In a wave that is traveling without reflection, characteristic impedance, or Z0, is the ratio of voltage to current. On a PCB, that line is a trace and the plane underneath it. Each millimeter contributes a small series inductance and a small capacitance to the plane, and the edge responds to the ratio of these.

The full expression is Z0 = √((R + jωL) / (G + jωC))

• R is the series resistance, and G is the leakage through the dielectric.
• L and C are inductance and capacitance, all per unit length.

Figure 2: Distributed inductance and capacitance along a PCB trace

The formula can be simplified to Z0 = √(L/C) at the frequencies at which the impedance is important; ωL is much larger than R, and ωC is much larger than G. That way, the meter will display R, and the edge will display L and C. Only if the delay of the trace is long compared to the edge, does the trace act like a PCB transmission line. A typical working limit is one-sixth of the rise time, one way.

Why Impedance Matching Matters for Signal Integrity

Wherever the impedance changes, part of the edge reflects toward the driver.

Figure 3: Reflection at a 50 Ω to 75 Ω impedance step

When a signal reaches a change in transmission-line impedance, part of the incident voltage wave may reflect toward the source. The voltage reflection coefficient gives the amplitude of this echo relative to the incident wave:

Γ = (Zₗ − Z₀) / (Zₗ + Z₀)

Where:

• Γ = Voltage reflection coefficient (dimensionless)
• Zₗ = Load impedance, or the impedance the wave encounters next (Ω)
• Z₀ = Characteristic impedance of the incoming transmission line (Ω)

For a 50 Ω trace connected to a 75 Ω section:

Γ = (75 − 50) / (75 + 50) = 25 / 125 = 0.20

Therefore, 20% of the incident voltage-wave amplitude is reflected toward the source. The positive sign indicates a non-inverted reflected voltage wave. This percentage refers to voltage amplitude, not reflected power.

What Determines PCB Characteristic Impedance?

Z0 is determined by 4 quantities on a finished board, and each of these quantities moves Z0 in a known direction. The first 3 are trace-filled, and the fourth is stackup-filled.

• The wider the trace, the less Z0 will be.
• Copper thickness: Thicker copper slightly reduces Z0.
• Dielectric constant (Dk): A larger Dk reduces Z0 and slows the edge.
• Dielectric height: An increase in the distance to the reference plane increases Z0.

Trace Geometry and Dielectric Properties

The greater the trace width, the more capacitance per unit length of trace because more copper is exposed to the plane. This results in a fall in Z0. The thicker the copper, the less the same way is pushed, since the sidewalls contribute to some extent to the coupling. Therefore, a 50 Ω trace on 1 oz copper will be drawn slightly narrower than a 50 Ω trace on 0.5 oz copper.

Dielectric Constant, Dk, is an expression of how effectively the laminate stores the electric field, relative to air. Capacitance is proportional to Dk, and Z0 is approximately inversely proportional to the square root of Dk. The range of FR4 varies from approximately 3.9 to 4.5, depending on the resin content, the type of glass, and the frequency. As the PCB dielectric constant guide shows, that will mean one drawn width will span two different FR4 grades.

For a classic closed-form estimation of a surface microstrip, it is:

• Z0 ≈ (87 / √(Dk + 1.41)) × ln(5.98h / (0.8w + t))

Here, h is one-unit dielectric height, w is trace width, and t is copper thickness, all in one unit.

PCB Stackup and Reference Planes

Dielectric height, or how far away the trace is from its plane, is the most powerful influence in the stackup. The higher the height, the greater the log, and so the greater the z0, and a thin dielectric, a narrow trace. On a two-layer board, the plane is a full core away, and a 50Ω microstrip is close to 2.8mm (110mil) wide. It shrinks to approximately 0.35 mm (14 mil) over the thin outer prepreg atop a four-layer board.

Figure 4: Cross-sections of the four common controlled impedance structures

The position of the plane is as important as the distance; an outer-layer trace has laminate below and air above, and its effective Dk is less. A stripline between two planes is completely covered by a laminate, resulting in lower impedance for the same width. Board thickness and layer count: Set your impedance options at the beginning so you can get them sorted out as you decide on your PCB thickness.

How PCB Impedance Control Is Achieved in Manufacturing

Impedance control is a joint responsibility of the PCBs. You tell the fabricator the target geometry, and he adjusts the width and dielectric to keep them within tolerance so the finished board meets the target.

Designing Controlled-Impedance Traces and Stackups

Controlled impedance begins at the stackup – not the trace. Start with the fabricator's normal prepreg thickness, since the calculator assumes a normal prepreg thickness and Dk. Once you have determined the widths you are going to use and need a custom stackup, you may end up paying for the lead time and, typically, the price.

1. Choose the stackup from the fabricator's standard list, so dielectric heights and Dk are known.
2. Assign a reference plane to every controlled layer, and keep it unbroken under the routes.
3. Calculate the width and gap for each target with the fabricator's calculator or a field solver.
4. Create net classes in your EDA tool, so the router holds those widths and gaps automatically.
5. List every target on the fabrication drawing, with its layer, width, reference plane, and tolerance.

However, when using differential pairs, there is one additional variable: the space between the two traces. As the gap decreases, the coupling increases, and the differential impedance decreases. Thus, width and gap are always solved simultaneously. Maintain the same gap throughout the track, as this means the pair temporarily becomes a pair of single-ended lines around a pad. Length matching is part of the guide to differential pair routing practices.

Controlling Materials and Manufacturing Dimensions

The main control parameters of a fabricator are the finished trace width and the pressed dielectric thickness that control the impedance. The copper beneath the etching is undercut, so the trace is narrower at the top than at the bottom. To make up for this, the CAM engineer spreads the artwork out. In addition, prepreg resin will seep into the spaces between copper features; therefore, the dielectric under a trace depends on the surrounding copper.

JLCPCB's impedance tolerance is ±10%, and according to its capabilities page, controlled impedance is only available for 4 layers or more. The JLCPCB impedance calculator is based on the real prepreg and core thicknesses of their standard stackups.

Impedance Testing and Quality Verification

A time-domain reflectometer (TDR) is used to measure impedance. It initiates a rapid step into the line and then measures the resulting voltage. Time on the trace corresponds to distance, yielding a plot of impedance vs. position. Few fabricators question your product lines. Instead, they measure a test coupon in the border of the panel, which is also made from the same layers and pressed in the same cycle. Thus, it has the same width and dielectric errors as your boards.

Figure 5: TDR trace of an impedance test coupon

This coupon trace, shown in a guide to PCB impedance testing using TDR, demonstrates that the reading is taken on the flat part of the trace away from the probe launch and the open far end. Passing out a coupon is proof of the process, but it is not about your layout. It does not apply to vias, connector pads, neck-downs, and plane gaps. Those features require simulation or board testing with a TDR if the link fails. Request the impedance test report from your fabricator and compare it with the impedance targets on your drawing.

When Does Controlled Impedance Matter?

When the edge is fast relative to the route, then controlled impedance is important. That's not necessarily determined by the clock frequency alone – a slow bus with sharp drivers might require it; a long, gentle I2C line might not.

High-Speed Digital Interfaces

All high-speed serial standards define a channel impedance. It is what your traces need to meet, as all the connectors, cables, and on-chip terminations are designed to that number. The targets have a small spread, meaning the stackup remains fairly simple despite the list of interfaces.

RF and Other High-Frequency Applications

All antennas, SMA connectors, filters, and test equipment are built to 50 Ω single-ended; that's why the standard RF design is as it is. A trace that rolls to 60Ω in front of the connector will reflect 9% of the voltage. This reflection is directly apparent as poorer return loss and lower power at the antenna. These lines are often routed on many RF boards as grounded coplanar waveguides. The ground copper is present on both sides of the trace and is stitched to the plane below with a row of vias. The side grounds pull the field inwards, allowing the line to remain narrow enough to accommodate a small IC pad.

The via fence is also used to stop coupling with other lines, but it introduces another dimension to maintain. At frequencies above a few gigahertz, the laminate itself begins to impose limits on you. The higher the frequency, the greater the signal loss per centimeter for FR4. The Dk also varies with frequency and glass weave type, causing impedance to vary from one panel to another. Many 5.8 GHz designs thus switch to Rogers RO4350B, which has a loss tangent of only 0.0037 at 10 GHz, approximately one-fifth of that characteristic of typical FR4 designs.

FAQs About Characteristic Impedance

Conclusion

The characteristic impedance depends on your PCB's physical design. Impedance is influenced by trace width, copper thickness, dielectric height, and dielectric constant (Dk), and a continuous reference plane ensures consistent signal behavior. If you picked your stackup early on, you should be able to determine the trace widths you need and use them as a guide throughout the layout. This means that impedance control is part of the design process, not something that needs to be corrected at the manufacturing stage.

When the rise and fall times of the signals are small, even fairly short PCB traces can act as transmission lines. This makes controlled impedance an important role in modern PCB design. With your stackup and trace width sorted, JLCPCB can produce controlled-impedance multilayer boards with an impressive ±10% tolerance. The same stackups can also ensure that your design calculations are consistent with the materials and dimensions used for your fabrication.