How to Choose and Place Decoupling Capacitors for PCB Design

Every digital PCB depends on decoupling capacitors, yet a surprising number of boards still suffer from voltage dips, glitches, and electromagnetic interference (EMI) issues caused by one simple mistake: incorrect placement or selection.

This guide walks through what decoupling capacitors do, how to choose the right value, where to place them, and which layout mistakes to avoid, so your next board runs clean on the first try.

Key Takeaways

• Place one decoupling capacitor near each IC's power pin.
• Use 100 nF X7R Multi-Layer Ceramic Capacitors (MLCCs) for most digital circuits.
• Pair local decoupling with a bulk capacitor near the power supply.
• Keep current loops and trace lengths as short as possible.
• Always follow the specific IC datasheet guidelines.

What Is a Decoupling Capacitor?

A decoupling capacitor is a small capacitor placed directly across an integrated circuit's (IC) power and ground pins. It acts as a local energy reservoir, supplying instantaneous current during switching events and filtering high-frequency noise from the power rail. In the PCB industry, it is often abbreviated as "decap."

A decoupling capacitor provides a nearby source of charge whenever an Integrated Circuit experiences a sudden current demand. By supplying this transient current locally, it helps maintain a stable supply voltage. Its primary functions are to:

• Supply instantaneous current during high-frequency switching events.
• Reduce voltage droop on the power rail.
• Filter high-frequency switching noise.
• Improve overall power integrity across the Power Distribution Network (PDN).

Figure: Decoupling capacitor connected in parallel across an IC's power and ground pins.

Why Do Integrated Circuits Need Decoupling Capacitors?

Digital ICs switch internal transistors millions or billions of times per second. Each switching transient causes a sudden current demand. Because every trace and via on a board has parasitic resistance and inductance, this sudden demand creates a brief voltage drop on the supply rail.

Without proper decoupling, a PCB may experience:

• Voltage droop and ground bounce.
• Signal integrity problems (jitter, ringing, crosstalk).
• Increased EMI radiating from power traces acting as antennas.
• Random microcontroller resets or unpredictable logic errors.

A decoupling capacitor absorbs this transient demand before it reaches the rest of the board, keeping the electrical disturbance local instead of system-wide.

Figure: Showing a current spike, a decoupling capacitor supplying charge, and the resulting stable voltage.

How Does a Decoupling Capacitor Work?

During switching, the IC briefly draws current from the nearby capacitor instead of the main power supply. Once the transient passes, the capacitor recharges from the supply rail. Because the capacitor sits physically close to the IC, it responds far faster than the longer return current path back to the voltage regulator.

Decoupling Capacitor vs. Bypass Capacitor

The terms decoupling capacitor and bypass capacitor are often used interchangeably, and in most practical designs, a single MLCC performs both jobs. However, they serve slightly different theoretical roles.

In modern digital design, one 100 nF ceramic capacitor at each IC power pin usually covers both roles. For a deeper breakdown of when the routing and layout distinctions actually matter, you can refer to the definitive guide to bypass capacitors in PCB layout.

How to Choose the Right Decoupling Capacitor

Selecting a decoupling capacitor comes down to five parameters: value, dielectric, voltage rating, package size, and self-resonant frequency.

Capacitance Value

• 100 nF (0.1 uF): Standard local decoupling value for most digital logic ICs, microcontrollers, and logic gates.
• 1 uF: Mid-frequency support, often paired alongside 100 nF on noise-sensitive or mixed-signal supply rails.
• 10 uF and above: Bulk capacitor for slower, larger current transients across a whole rail or board segment.

Dielectric Type

• X7R: Stable across temperature (minus 55 to plus 125 degrees Celsius), the standard choice for general digital decoupling.
• X5R: Similar to X7R with a narrower temperature range (minus 55 to plus 85 degrees Celsius), common in compact consumer electronics.
• C0G/NP0: Highly stable and precise, but low capacitance per package size. Typically reserved for analog filters or RF circuits rather than power supply decoupling.

Voltage Rating

Always select a voltage rating with headroom above the rail voltage. Ceramic capacitors lose effective capacitance as DC bias approaches their rated voltage (known as DC bias aging), sometimes by 60 to 80 percent. A 10 V or 16 V rated capacitor on a 3.3 V or 5 V rail keeps actual capacitance close to the labeled value.

Package Size

• 0402: Compact, used in dense high-speed PCB designs; slightly higher cost and harder to hand-solder.
• 0603: Common balance of size and cost for most digital boards.
• 0805: Easier to hand-assemble or rework, used where board space is generous.

While through-hole capacitors were once common, modern designs favor surface-mount devices due to their vastly superior high-frequency performance and minimized parasitics. You can read more about this in our comparison of surface-mount technology vs through hole.

Self-Resonant Frequency (SRF)

Every real capacitor has parasitic inductance from its leads, internal structure, and mounting traces (Equivalent Series Inductance, or ESL).

Below its self-resonant frequency, the capacitor behaves capacitively, and impedance falls as frequency rises. Above the SRF, that parasitic inductance dominates and impedance rises again, so the capacitor stops decoupling effectively. Smaller capacitance values and smaller packages generally have lower ESL and therefore a higher SRF.

This is the core reason designs combine multiple capacitor values: a 100 nF capacitor remains effective at higher frequencies where a typical 10 uF capacitor has already passed its self-resonant frequency, and the 10 uF capacitor covers lower frequencies the 100 nF cannot supply.

Even a capacitor with an ideal SRF performs poorly if decoupling capacitor placement puts it too far from the IC, so component selection and PCB placement always work together.

Figure: Impedance versus frequency chart comparing a 10 microfarad capacitor and a 100 nanofarad capacitor, showing each capacitor's self-resonant frequency dip.

Why is 100 nF the Most Common Decoupling Capacitor Value?

100 nF became the industry standard because it:

• Provides good high-frequency performance in a small package.
• Fits easily into compact MLCC packages with low parasitic inductance.
• Is highly inexpensive and widely available across every footprint.
• Works well as a general-purpose value for most digital ICs.

However, high-speed processors, FPGAs, and System-on-Chips (SoCs) often require additional 1 uF and bulk capacitors to cover the lower-frequency transients a single 100 nF capacitor cannot supply. For this reason, 100 nF remains the default starting point for digital decoupling, with additional capacitance added only when required by the application's power demands.

Find the Right MLCCs

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How to Place Decoupling Capacitors Correctly

Proper placement of decoupling capacitors is just as important as selecting the correct capacitance value. Placement determines whether a correctly sized capacitor actually works.

Place Close to IC Power Pins

Keep the capacitor within a few millimeters of the IC's power pin. Distance adds trace inductance, and inductance is exactly what defeats high-frequency decoupling.

Keep Traces Short

Short, direct traces from the capacitor to the power and ground pins minimize parasitic resistance and inductance along the current path.

Minimize Current Loop Area

The loop formed by the power pin, the capacitor, and the ground connection should be as small as physically possible. A smaller loop radiates less EMI and presents lower inductance. Poor decoupling capacitor placement increases loop inductance and reduces high-frequency effectiveness.

Connect Directly to the Ground Plane

Route the capacitor's ground pad straight down to the ground plane with the shortest possible return current path. Avoid routing the ground connection through several layers or long traces.

Use Dedicated Vias

When a via is required between the capacitor pad and the plane, use a dedicated via placed as close to the pad as possible, and use multiple vias in parallel where space allows to reduce inductance further.

One Capacitor per Power Pin?

Many modern ICs, especially FPGAs and high-pin-count microcontrollers, have multiple power (VDD) pins. As a general rule, place one local decoupling capacitor per power pin unless the datasheet explicitly states that pins share an internal plane.

Figure: PCB layout comparison of correct close placement versus incorrect distant placement of a decoupling capacitor.

Decoupling Capacitor Layout Recommendations for Different PCB Types

Bulk Capacitor vs. Local Decoupling Capacitor

A complete power distribution network needs both capacitor types working together, not one in place of the other:

• Bulk capacitor: Supports slow, high-energy current changes across an entire supply rail, typically 10 to 47 uF or higher near the power input or regulator output.
• Local decoupling capacitor: Handles fast-switching transients at each IC; typically 100 nF, sometimes with an added 1 uF.
• Together: They provide low impedance across a broad frequency range, from low-frequency rail changes up through fast digital switching events.

Figure: Power flow diagram from input through a bulk capacitor to an IC with a local 100 nF decoupling capacitor.

Common Decoupling Capacitor Mistakes to Avoid

Figure: PCB layout highlighting common decoupling capacitor placement mistakes.

Typical Decoupling Capacitor Configurations for Popular MCUs

Most MCU manufacturers recommend placing a local ceramic decoupling capacitor adjacent to every supply pin, with exact values specified in the device hardware design guidelines.

Figure: Example PCB layout showing a 100 nF decoupling capacitor placed next to an STM32 VDD pin with a short via to the ground plane.

Decoupling Capacitor Design Checklist

• Place the capacitor within a few millimeters of the power pin.
• Keep power and ground traces as short and wide as possible.
• Connect directly to a solid ground plane to minimize the return current path loop.
• Use X7R or X5R MLCCs for general digital decoupling.
• Add a bulk capacitor near the regulator or power entry point.
• Always follow the IC datasheet's recommended values and placement.

Conclusion

Selecting the correct capacitance is only half the job. Low-ESL MLCCs, short PCB traces, solid ground planes, and datasheet-recommended placement work together to create a stable power distribution network. Following these practices improves signal integrity, reduces EMI, and increases the reliability of both simple microcontroller boards and complex high-speed digital systems.

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