Demystifying Bare PCB Quality for Reliability-Critical Applications

A bare PCB is your last chance to catch a fabrication defect before it becomes an expensive assembly failure. Fixing a small fault at this stage may cost only the board. Once components are soldered, the same fault can waste parts, demand rework, and delay the build. This final fabrication checkpoint therefore, deserves your careful attention before component assembly begins. Copper thickness, laminate properties, surface finish, and electrical testing determine whether the finished board assembles correctly and keeps working throughout its service life.

In this guide, you will learn:

• What a bare PCB is, and where it sits between fabrication and assembly
• Why a zero PCB is not a substitute, and where it stops working
• Copper weight, laminate Tg, Td, and CTI, in numbers, you can check
• Surface finish thickness and shelf life, finish by finish
• How bare board testing finds opens and shorts that your eyes cannot
• What AOI catches, what electrical test catches, and what neither does

Understanding the Essence of a Bare PCB

Picture a city whose roads and junctions are finished before traffic arrives. A bare PCB is similar: its copper routes, holes, and protective coatings are complete, but no components carry current yet. The assembly adds those parts and activates the designed circuit.

What is a Bare PCB and Where Does It Fit in Product Development?

A bare PCB is the completed board before assembly adds any components. The factory has already built its conductive paths and protective layers; you or the assembly line supplies the parts later.

Strip one down, and you find six layers of work:

• The substrate, usually FR-4, woven glass cloth, is soaked in epoxy and cured hard
• Etched copper, on the outer faces and any buried inner layers
• Plated through holes, copper barrels carrying signals side to side
• Solder mask is the coating that keeps solder off everything but the pads
• Silkscreen, the white legend printing designators, and polarity marks
• A surface finish, a thin protective coating over the exposed copper

This handover marks the end of fabrication and the start of assembly, making it your last inexpensive checkpoint. A two-layer bare board can cost two dollars.

Bare Board vs. Zero PCB: Moving Beyond Perfboard Prototyping

A zero PCB is not a blank version of your design. It is a general-purpose board with no design in it at all: a grid of isolated holes on 2.54 mm (100 mil) pitch, each ringed by a copper pad. It is also called a perfboard or dot matrix board.

Three elements are missing, and each poses a practical issue:

1. No plated through-holes: Copper foil is only bonded on one side of the pad. Repeat this process several times, and the adhesive may become softened, allowing the pad to come up with the part.
2. No solder mask or silkscreen: Pads are bare, making it easier to bridge closely spaced joints; no markings mean there is no identification of parts or holes.
3. No copper connections: All connections need to be made with wires, which have their own resistance, inductance, etc.

Let’s put on exact figures: A piece of wire, for example, 50 mm (2 inches) of 30 AWG wire has about 60 nH of inductance. That inductance can generate approximately 0.6 V of noise on the power rail if the current changes by 20 mA in 2 ns. That is a big blow to the logic margin on a 3.3 V board. If a PCB trace is laid over a ground plane, the inductance will be reduced to approximately 15-25 nH, and a power plane can further reduce the inductance to below 1 nH.

So a zero PCB stops being viable at four points:

1. Above roughly 10 to 20 MHz, with no reference plane and no controlled impedance.
2. Below 1.27 mm (50 mil) pitch, because the grid is fixed at 2.54 mm (100 mil).
3. Above one or two amps, where current runs through a hand joint instead of a copper pour.
4. Beyond one unit, because each takes hours and no two come out identical.

Stripboard, or Veroboard, sits in between. Continuous copper strips remove some wiring, and it still has no plated holes, no mask, and no plane. See our PCB design rules guide.

Essential Production Quality Indicators for Unpopulated Boards

Appearance alone cannot confirm bare-board quality. Two boards may look identical yet differ twofold in copper thickness, resin quality, or coating thickness, and each difference changes reliability throughout normal service.

Substrate Integrity, Copper Weight, and Layer Adhesion

Start with copper weight, the number most often misread. One ounce means one ounce of copper spread over one square foot, which is 35 microns (1.4 mil) thick. Half an ounce is 17.5 microns (0.7 mil), and two ounces is 70 microns (2.8 mil). On the outer layer,s the factory starts with thinner foil and plating brings it up, so "1 oz outer" is a finished thickness rather than a starting one. The number worth checking is the copper inside the hole: IPC-6012 asks for 20 microns (0.8 mil) average in the plated barrel for Class 2, and 25 microns (1 mil) for Class 3.

Three laminate numbers tell you what the substrate survives:

• Tg, the glass transition temperature: Above it, the resin softens and expands through the board thickness several times faster, which pulls the barrels apart. Standard FR-4 sits at 130 to 140 degrees C and high Tg at 170 to 180 degrees C. Keep your hottest operating temperature 20 to 30 degrees C below it, and see how to select the Tg of a PCB.
• Td, the decomposition temperature, is the temperature at which the resin has lost 5% of its mass. Lead-free reflow peaks near 245 to 260 degrees C, so ask for Td of 340 degrees C or better on boards facing two or three passes.
• CTI, the comparative tracking index: The voltage a surface survives against 50 drops of contaminated water before a carbon track burns across it. Standard FR-4 lands near 175 to 250 V, and high-CTI grades reach 600 V, so a low CTI forces wider creepage gaps on mains circuits.

Layer adhesion is where IPC-A-600 does its work. Measling is white spots where resin pulled away from the glass weave, crazing is the same, joined into lines, and delamination is a full separation seen as a blister. All three are judged by how far they close the gap between conductors. Tg tells you what the board survives in service, and Td tells you what it survives in the oven.

Solderability and Protective Surface Coating Uniformity

Exposed copper starts oxidizing immediately, and solder will not wet oxide reliably. A surface finish protects each pad by blocking oxygen. A judge who finishes by its thickness and, equally important, the uniformity of its coverage across the panel.

Gold thicker than about 0.125 µm (5 microinch) can actually be a warning sign rather than an advantage. Too much gold can make the solder joint brittle, while the plating process can also attack the nickel underneath.

Thickness alone is not enough; coverage must also be uniform. Check pads across the panel, especially at the edges and center. A finish measuring 4 µm in the center but only 1 µm at the edge can pass an average reading while still causing assembly failures during solder paste printing and reflow.

The Crucial Role of Bare Board Testing

Bare board testing is the cheapest quality gate you will pass through. A defect caught here costs a board. Caught after assembly, it costs the board, the components, the placement time, and a slot in your schedule.

Eliminating Open and Short Circuits Prior to Component Placement

Bare board testing checks every design net in two complementary ways. Continuity confirms that intended connections exist. Isolation confirms that separate conductors remain electrically separate. Together, they expose hidden opens and shorts.

Those failures come from a short list of causes, and most are invisible:

1. A copper sliver from under-etching, bridging two traces that should never meet.
2. A scratch in the etch resist, thinning a trace until it opens.
3. A void in a plated via barrel, so the copper tube inside the hole is not continuous.
4. Drill breakout, where the drill wandered outside its pad.
5. Inner layer misregistration, shifting a buried layer against the drilled holes.

The cost of catching a defect roughly multiplies by ten at each stage downstream, and the bare board is the earliest stage. A board that fails here is scrapped. The same board found at the final test takes your components and your delivery date with it.

Electrical Continuity Testing: Flying Probe vs. Automated Bed-of-Nails

Before choosing a machine, answer the important question: what reference does the tester use to judge your board?

The right answer is an IPC-D-356A netlist, a text file your CAD tool exports alongside the Gerbers. It names every net and gives the location, layer, hole size, and access of every pad on it. Send it, and the shop tests your copper against your schematic. Send Gerbers alone, and the shop extracts a netlist from the artwork instead, which finds etching and drilling faults but can never tell you the artwork was wrong.  The older alternative is self-learning from a golden board: run a known-good first article through the tester and store its connections as the reference. The trap is obvious. If the golden board has a defect, every board afterward matches that defect and passes.

A dedicated fixture uses a separate spring probe for each test point on one specific board. A universal grid fixture uses a fixed bed of probes, typically from 2.54 mm (100 mil) down to about 0.64 mm (25 mil) pitch. A translator made from drilled plates then guides each probe to the actual pads on the PCB. The main difference is flexibility. With a universal fixture, only the translator plates change for each board. Both types make sense when the same PCB is tested repeatedly in production.

Electrical test cannot see:

• A barrel that conducts today but is 8 microns (0.3 mil) thick and will crack in reflow
• A trace necked to 60% of its drawn width, which passes continuity and still runs hot
• Solder mask misregistered onto a pad, or silkscreen ink printed across one
• Oxidation or contamination, so nothing about whether the solder will actually wet
• Controlled impedance, board thickness, warp, or outline dimensions

How JLCPCB Ensures Zero-Defect Bare PCB Manufacturing

AOI and electrical testing catch different bare-board defects. Automated optical inspection checks physical shape; electrical test checks connectivity. Omitting either one leaves an entire class of failures hidden until after component assembly begins.

High-Precision CNC Machining and Automated Optical Inspection (AOI)

Drilling accuracy makes everything downstream possible. Everything downstream is possible with drilling accuracy. JLCPCB is able to drill 0.15mm (6mil) diameter holes on 2-layer or higher boards, with a minimum finished via of 0.25mm (10mil), and they require at least 0.20mm (8mil) at 1 oz copper thickness for the hole annular ring; 0.25mm (10mil) is recommended. The collar of copper that remains around a hole after it has been drilled is the annular ring. Registration can wander by tens of microns across a panel, and a ring built to 0.05 mm (2 mil) may disappear on one side, and the connection hangs on a sliver.

AOI, or automated optical inspection, photographs the etched copper and compares every image with CAM data using pixel-by-pixel comparison across each layer. It catches defects that have a visible shape: slivers, nicks, pinholes, missing copper, spacing violations, and solder mask shifted onto a pad. JLCPCB runs AOI after pattern plating and checks inner layers before lamination, the last stage when a buried defect remains accessible.

100% Free Bare Board Testing for Enterprise-Grade Reliability

JLCPCB states that every board receives 100% AOI and electrical testing before shipment at no separate fabrication charge. Testing uses either flying probes or a bed-of-nails fixture. Both checks are included instead of being offered as optional line items. On a five-piece order of two-dollar boards, a test charge can represent much of the total, tempting buyers to decline it. The untested board can then consume a full day while you probe a circuit that was never at fault.

Check the remaining specification directly against your design. JLCPCB lists 1 to 32 layers on Grade A laminate from suppliers including Nan Ya, KB, and Shengyi. Trace and space start at 0.10 / 0.10 mm (4 / 4 mil) with 1 oz copper. Board thickness spans 0.4 to 4.5 mm (16 to 177 mil), with plus or minus 10% tolerance above 1.0 mm. Finish choices include HASL, lead-free HASL, ENIG, or OSP, and ENIG is required for 6-layer and RF builds.

Ready to Turn Your Design into a Finished Bare PCB?

Upload your Gerbers and your IPC-D-356 netlist together on the JLCPCB instant quote page, so the boards are tested against your schematic rather than your artwork. If you are assembling them too, check the JLCPCB parts library before finalizing footprints, and our guide to bare board quality control and testing covers the full inspection chain.

Specifically, Class 3 is not a checkbox that makes a board better. Against Class 2, it removes annular ring breakout entirely, where Class 2 tolerates up to 90 degrees of it behind a teardrop. It raises the average barrel copper from 20 microns (0.8 mil) to 25 microns (1 mil), and copper wrap onto the surface pad from 5 microns (0.2 mil) to 12 microns (0.47 mil). All three cost money and yield, so ask for Class 3 where downtime is unacceptable, not by default.

FAQ about Bare PCB

Conclusion

A bare PCB looks like the simplest part of a build, which is why price often dominates its purchase. Yet the delivered board can differ from your specification in barrel copper, laminate Td, or surface-finish uniformity. None of those differences is obvious from across a workbench, although each one can shorten the board's life.

Judge bare-board quality by evidence you can check: copper weight, barrel-plating class, laminate Tg, Td, and CTI, finish thickness, manufacture date, and confirmation of electrical testing against your supplied netlist. Send that netlist with your Gerbers. Choose the finish for the date you will assemble, not the date you design. This timing protects solderability during storage. That keeps bare board testing at the stage where a defect still costs two dollars.