GPT-6 Astra PCB Design in EasyEDA Pro: What Worked, What Failed, and What We Learned

Most discussion of GPT-6 Astra's PCB design capability has centered on a single demonstration using KiCad. Whether the same workflow could be reproduced in another EDA tool had not been publicly demonstrated.

On 10–11 September 2026, the test was conducted using a native EasyEDA Pro 3.2.149 installation and a four-line brief for a stereo Class-D amplifier. The finished board matters, but the more useful finding was the import failure that surfaced during verification.

In this review, you will see:

• The exact prompts used to start the project
• How the TPA3116D2 schematic was checked against the datasheet
• Why the first EasyEDA Pro import reported 50 association mismatches
• The File > Import > EasyEDA (Standard) workflow that successfully opened the project
• What EasyEDA Pro's built-in DRC can check — and what it cannot

What GPT-6 Astra Was Asked to Build in EasyEDA Pro

The brief was only four lines long, leaving most design decisions open.

GPT-6 Astra was given a 12 V single supply, stereo input and output, 4 Ω speakers, an all-SMD build, and a small-board requirement. It did not specify a topology, part number, or exact board size.

The reference folder contained one datasheet and two reference circuits, so the remaining design choices were left to the model.

The recorded opening prompt was:

• "Can you use the EASYEDA PRO opened on my computer to make a PCB? Can you access that?"

The requirements are met in a single message, so the wording below preserves the recorded prompt, including the folder path, as plain text.

• "In the TPA3116D2_PCB/ there are some design files and reference PCB design, first make the schematic."
• "My requirements are such that:"
• "I will use it with a 12V single power supply."
• "I need stereo input and output."
• "You have to use SMD components only for this design."
• "I will keep the PCB as small as possible when designing the PCB."

One question came back before any drawing started, because the speaker impedance was missing. The answer was "4 Ω per channel", which then set the output current, the filter values, and the cooling requirement together.

Tools Used in the GPT-6 Astra PCB Design Test

No single tool produced the board. GPT-6 Astra worked through a native EasyEDA Pro 3.2.149 installation in Half Offline mode, while KiCad 10.0.4 and a local copy of Freerouting 2.0.1 handled parts of the routing and export process.

This was one continuous project with repeated corrections, not a set of independent benchmark runs. The result is therefore best read as a case study rather than a score.

• GPT-6 Astra: Read the brief and the references, wrote & build scripts, planned placement, and reviewed each failure before correcting it.
• EasyEDA Pro 3.2.149: Held the editable native schematic, PCB, and embedded libraries, and ran the final native DRC.
• KiCad 10.0.4: Carried the routed manufacturing master, filled the copper zones, and exported the fabrication files.
• Freerouting 2.0.1: Routed the remaining low-current connections once the critical copper had been defined and locked.

The routed master board was first built in KiCad and then imported into EasyEDA. This workflow matters because the imported board structure affects how the ground copper is handled in EasyEDA later. The board construction process, including the scripted build and the issues encountered with the KiCad Python API, is covered in our companion guide, GPT-6 Astra PCB Design in KiCad.

This workflow also requires more than a standard chat interface. The test environment needs access to local files, application control, and locally installed EDA tools, so the tool setup itself is part of the methodology. For comparison, our Flux.ai PCB design walkthrough uses a different tool environment and workflow.

GPT-6 Astra PCB Design in EasyEDA Pro: A Real Test

Before You Start

• A desktop agent environment with file access and application control. A normal chat window cannot drive EasyEDA Pro from a prompt alone.
• EasyEDA Pro is installed and open, plus any routing and export tools you intend to use.
• One project folder holding the datasheet and any reference circuits.

10-step quick workflow

1. Collect the reference files into a single project folder and point GPT-6 Astra to that folder.
2. Provide the full electrical brief in a single message: supply voltage, channel count, load impedance, component technology, and size limit. A missing load impedance prevents the run from starting.
3. Ask that the supplied reference be checked against the current datasheet revision rather than copied, because reference images and older datasheets contain errors.
4. Have the schematic built in EasyEDA Pro, then verified pin by pin against the circuit specification, including any intentional no-connect.
5. Verify footprints before layout: pin 1 position, pad numbering, polarity, rotation, and an orderable part behind each one.
6. Set the design rules to the values you will actually order against, then ask for placement inside a fixed board outline.
7. Route the critical copper first, covering supply, bootstrap, and switching outputs, and lock that geometry before any autorouter runs.
8. Give every footprint a unique name and identifier before importing, because shared library names merge in the device cache and quietly swap pad orientations.
9. Import with File > Import > EasyEDA(Standard), review the schematic-to-PCB changes before applying them, then save and run the native DRC.
10. Export the release and check it against your manufacturer's capabilities. A clean DRC reports only the rules you enabled, so it is not a manufacturability check.

Checking the Reference Design Against the TPA3116D2 Datasheet

The supplied reference was treated as something to be verified rather than simply copied. A comparison with the current datasheet identified two circuit details that needed correction, plus one package-related issue.

The first step was to correct three issues:

• Input coupling: The reference uses 1 nF, while this board uses four matched 2.2 µF capacitors on both inputs and their references.
• Bootstrap pairing: Taken from TI datasheet revision G, because the supplied copy predates the correction.
• Package: TPA3116D2DADR in the DAD0032A outline, which puts the exposed thermal pad on top.

Figure: The supplied TPA3116D2 reference schematic, drawn with 1 nF input coupling capacitors.

Building a TPA3116D2 Schematic with GPT-6 Astra in EasyEDA Pro

The schematic was drawn during this task rather than imported from the reference. It splits the amplifier into seven blocks and ties every symbol pin to a named net. The PCB can then be checked against the same specification.

Figure: The completed schematic groups the stereo inputs, supply, amplifier, control circuit, and four output-filter legs.

Input, Gain, and Control

• Four 2.2 µF capacitors couple both signal inputs and their ground references, while the two reference capacitors return to the input ground near J2. R2 sets the master gain at 20 dB through a 5.6 kΩ strap.
• SDZ and FAULTZ are tied together and pulled to +12 V through 100 kΩ, because that is the automatic fault-recovery arrangement TI describes. Pulling the shared net low through TP1 shuts the amplifier down.
• MUTE is held low for normal operation, while PLIMIT is tied to GVDD. SYNC pin 16 is intentionally unconnected and carries a no-connect flag, so a later check can confirm that no wire reached it.

Supply Bypass and Output Filters

The amplifier uses BD modulation at 400 kHz, selected by grounding the MODSEL and AM pins. From there, the supply and output-stage components fall into four main groups:

• Bootstrap: Four 220 nF capacitors, each running from one bootstrap pin to its own switching output.
• Bulk bypass: Two 100 µF 25 V low-ESR hybrid capacitors, one above and one below U1.
• Local bypass: 100 nF and 1 nF ceramics at each PVCC end, a separate 100 nF at AVCC pin 17, and 1 µF on the internal GVDD rail.
• Output filter: 10 µH into 680 nF on each of the four legs, followed by a 1 nF bypass and a 3.3 Ω plus 10 nF damping branch.

These values were chosen specifically for this board, supply voltage, and load. They are not a universal Class-D design recipe. Change the supply, speaker impedance, or switching frequency, and the appropriate component values will change accordingly.

The schematic review also went beyond simply counting symbols, because a symbol count says little about whether the circuit is actually wired correctly. The connections were reconstructed from pin positions, wire traces, and net labels, and then checked against the intended circuit specification.

That established the baseline for the rest of the design: 45 component instances, 120 pins, and 28 nets.

The 45 instances include the wire pads and test pad, so they should not be confused with the 40 physical parts that are actually purchased and assembled on the board.

Verifying PCB Footprints Before Layout

Correct wiring establishes nothing about the copper, because the netlist never sees a pad. Pad numbering, package dimensions, polarity, and rotation all had to stay correct as those symbols became PCB components.

The verification list covered:

• U1 pin 1 position and all 32 pad numbers.
• Positive and negative pads on the polarized bulk capacitors C10 and C11.
• Pad order after rotating the input, control, and output components.
• Surface-only wire pads with no drilled hole and no paste aperture.
• Matching symbol, device, and footprint associations across all 45 instances.

Turn Your Verified Design into a PCBA

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• Each footprint should also correspond to a real, orderable component. Verifying the package specification and component availability in the JLCPCB Parts Library early can help ensure the footprint matches a component available for assembly and avoid unnecessary footprint changes later.

• Once your footprints and component choices are verified, move from PCB design to assembly with JLCPCB.

PCB Placement and Routing in a 44 × 34 mm Board

Placement set the signal flow before routing began, so the copper had a direction to follow. Inputs and controls stay on the left, U1 sits in the center, and the inductors and speaker pads occupy the right.

Figure: The assembly map shows input pads on the left, U1 in the center, four inductors on the right, and the reserved top heatsink area.

Signal Flow Across the Board

The inductor order follows the amplifier output pin order, which keeps the switching routes from crossing. The bulk capacitors sit above and below U1, while the local ceramics cluster around their supply pin groups.

The analog inputs stay on the quiet left side, away from the switching output area. That separation matters more when the board is compact, because the switching nodes and the input pins end up millimeters apart.

Placement had to balance several competing requirements:

• Keep the bootstrap and supply-bypass connections short.
• Give the four output paths room to reach their inductors.
• Preserve a usable ground return across the whole board.
• Leave clearance for the top heatsink and the two polarized capacitors.
• Keep the external wire pads reachable at the board edges.

Trace Widths for Power and Signal Routing

The board uses 0.25 mm signal traces, 0.35 mm switching escapes near U1, about 1 mm output traces, and a 2 mm supply trunk. These widths suit this board and its 1 oz copper; they are not universal current limits.

Traces were widened wherever pin spacing allowed. The supply route could also pass under U1 because this package has no exposed thermal pad. The board has 51 plated holes, all used as vias.

There are no mounting holes, keeping the design fully SMD and leaving mechanical mounting to the enclosure. Once the board outline was stable, a quick two-layer FR-4 quote made it easy to check the cost impact of board size before finalizing the layout.

Why Did the First EasyEDA Pro Import Fail?

The first complete import opened normally and looked correct, but the library links were inconsistent. A separate native check reported 50 association mismatches, even though all 120 PCB pad nets were counted correctly.

What the First Native Check Reported

Of the 50 warnings, 20 were footprint mismatches, and 30 were schematic-to-PCB mismatches, all involving repeated component types.

The cause was a shared library name: every 0603 capacitor used C0603, so EasyEDA Pro merged footprints that should have remained separate. Synchronization reduced the warnings from 50 to 20, but did not fully fix them. The key point is that pad net names can remain correct even when the physical footprint association is wrong. That is why all 120 pad nets checked out, while the imported board still had hidden problems.

Fixing the Footprint Association Mismatch

The fix was to give each imported footprint a unique name and ID while keeping it linked to the schematic. For example, C12 became C0603_C12 and R4 became R1206_R4.

After rebuilding and reimporting the schematic-PCB pair, the native check returned 45 parts, 120 pins, 28 nets, and zero errors.

How to Import an EasyEDA (Standard) Project into EasyEDA Pro

The import itself is simple. What matters is the order of the checks before and after it.

1. Open File > Import > EasyEDA(Standard).
2. Select the ZIP holding both the schematic JSON and the PCB JSON.
3. Choose Import Document and Use source file style.
4. Keep automatic footprint association enabled and automatic 3D-model association disabled for this import.
5. Create the project, open its PCB, and review the schematic-to-PCB changes before applying them.
6. Save the synchronized project and run DRC again.

The final synchronization updated names and channel data without moving any verified pads. It also cleared the generated net name from the unused SYNC pad. Solder-mask expansion was set to 0.05 mm per pad edge. Paste was disabled on the wire and test pads, so the stencil applies solder only to fitted SMD components.

What the Native EasyEDA Pro Checks Reported

The final checks compared the saved schematic and PCB data directly, covering connections, pads, traces, vias, and ground regions before running the native DRC.

Figure: TPA3116D2 audio amplifier PCB top copper layout showing local ground clearances and four filtered output paths

Figure: TPA3116D2 audio amplifier PCB bottom layer, staying almost entirely ground copper with short routes and vias on the quiet input side

The Saved Design Checks

One important change was documented: EasyEDA dropped a ground segment shorter than 3 µm because its endpoints already overlapped the same-net copper. Connectivity and DRC still passed.

The ground copper was imported as fixed filled regions. If components move, those clearances will not update automatically.

Two options remain:

• Refill the KiCad master and reimport.
• Replace the fixed regions with native EasyEDA copper areas and rerun DRC.

What the Final Release Contains

• TPA3116D2_COMPLETE_REV_A.eprj2:The native EasyEDA Pro schematic, board, and embedded libraries.
• TPA3116D2_Gerbers_44x34mm.zip: Copper, mask, silkscreen, paste, outline, and drill files from the checked master.
• PCB_BOM.csv and PCB_PickAndPlace.csv: Component requirements and placement coordinates for the 40 fitted parts.
• PCB_Assembly_Top.pdf and the schematic PDF: Assembly and circuit references.
• The KiCad board, project settings, and local footprint library: an editable master with refillable ground zones.
• Verification reports and a release manifest: The recorded checks, file sizes, and file hashes.

Why a Clean DRC Is Not a Manufacturability Check

DRC only confirms that the layout complies with the rules set by the design tool. It does not prove that a specific factory can manufacture the board. No DFM upload, factory review, or order was completed in this project, so manufacturability remains a next-step check.

Figure: Side-by-side render of TPA3116D2 audio amplifier PCB top and bottom layers, showing component routing and the bottom ground plane

What to Check Before Manufacturing

1. Compare the release against the PCB capabilities and assembly capabilities you intend to order.
2. Review layer assignment, outline, drills, mask, paste, copper weight, and panel handling.
3. Run the exported files through a factory-oriented analysis, such as the free DFM tool.
4. Confirm orderable part numbers, MLCC voltage ratings, and capacitor polarity against the BOM and the assembly drawing.
5. Fit a suitable top heatsink with electrical clearance from the IC leads, then power up from a current-limited 12 V bench supply.

Conclusion

GPT-6 Astra turned a four-line brief into an editable EasyEDA Pro project, a routed PCB, and a checked release package. The more important result, however, was finding that a board can open normally and still contain 50 broken library associations. That is why the saved schematic, PCB data, connectivity, and DRC results matter more than a successful import message.

The 2 × 50 W headline rating of the TPA3116D2 should also not be treated as the output power of this board. At a 12 V supply and a 4 Ω load, the real output depends on the available supply current, cooling, and the acceptable distortion level. Those limits were not measured in this project.

The design is therefore electrically checked, but not yet factory-verified. The next step is a proper DFM review against the manufacturer's fabrication and assembly limits before the board is released for production.

FAQs about GPT-6 Astra and EasyEDA Pro