Understanding the Frequency Response of Decoupling Capacitors

Decoupling capacitors act like mini “shock absorbers” or local reservoirs on an IC’s power pins. Decaps are used to isolate high‐frequency AC noise from the DC supply. These decaps supply instant current during transients. When it comes to transient switching, the sudden change of voltage drops the current, and to fulfill the demand of that loss, the current is supplied from the source, which is situated away from the IC. But due to the resistive path between the IC and the supply, the frequency response shows worse characteristics. That’s why a decap is used just closer to IC.

In simpler terms, they provide a low-impedance path to ground for fast spikes and help keep a chip’s voltage steady during sudden demand. Imagine them as tiny batteries that deliver juice right at the gate of your microcontroller or FPGA, rather than having to draw it all the way from the power entry point.

What |Z| vs Frequency Gives:

From these lessons, the goal is to achieve a smooth, low-impedance profile over frequencies. An impedance vs frequency plot is the engineer’s map. The valleys (where |Z| is low) show where decoupling is effective, and peaks indicate trouble spots. The valleys are due to the capacitive poles, and when the frequency increases, the zeros of the circuit become active due to the parasitic inductances.

Resonant Peaks in Decoupling Capacitors:

The resonant frequency is given by ω₀ = 1/√(L·C). Below f₀, the cap effectively shunts noise to ground, but beyond f₀, its parasitic inductance (ESL) makes it behave like an inductor, and its impedance grows again. In practice, every real capacitor has some ESR (series resistance) and ESL. From a frequency perspective, a decoupling cap is ideally short at high frequencies and open at DC. Below its self-resonant frequency, the cap “looks” like a pure capacitance, as we know the impedance is given by 1/(ωC, and above that it becomes inductive (impedance rising with ω because of the parasitic lead inductance).

Due to the ESL and ESR, the magnitude of its impedance |Z| vs frequency follows a characteristic curve. It falls roughly 20 dB/decade (capacitive) until reaching a minimum set by ESR, and then rises (inductive) at higher frequencies. In short, the minimum impedance of a cap is dictated by its ESR, and the high-frequency rise is dominated by its ESL. Designers therefore seek low-ESR capacitors for the lowest impedance floor, but note that a very low ESR can produce a very sharp resonance peak (high Q).

Practical Decoupling Guide:

Usually, it requires several values of capacitors in parallel. A large capacitor (electrolytic, tantalum, or polymer, e.g, 10–100 µF) provides a charge reservoir for low-frequency transients, while small ceramic caps (e.g.,0.1 µF or 0.01 µF) handle very fast noise.

For example, it is recommended to have ne bulk capacitor (~10 µF) at the board entry and local decoupling (~0.1–1 µF) at each IC. Overall response now carries a resistive path between the local decoupling and board entry capacitor, which somehow increases the overall ESR, and we will get a constant frequency to impedance profile. Lower C or lower L gives a higher self-resonance, so using small, multi-layer SMD capacitors and minimizing trace/via inductance pushes f₀ higher and widens the useful band.

Layout Guidelines to Decoupling Capacitors:

All decoupling caps should connect directly to a low-impedance ground plane via very short traces or vias. Do you know why? Because a low impedance return path allows the current to sink and source faster, and provides no inductor behaviour at all. The closer and wider the copper loops, the lower the ESL. For instance, placing a 0.1 µF cap right across the power pin and ground pin of an IC (with minimal lead length) is much more effective than a long trace to a distant capacitor. Multi-via connections are often used to further reduce inductance, and designers even recommend matching the capacitor's ESR to the IC's impedance.

Adding Capacitors in Parallel for Better Decoupling:

Multiple caps in parallel do not simply add like resistors; their resonances interact. A common strategy is indeed to combine, say, four 0.1 µF caps with one 10 µF cap. The 10 µF’s self-resonance might be at a few hundred kHz, while each 0.1 µF might resonate around tens of MHz. Their parallel combination thus creates two (or more) impedance minima, extending effective decoupling across a wide band. Where there are lower peaks than the minimum impedance, there is no issue, but an unwanted high impedance peak can also be seen when doing this practice (up to 150 Ω). In other words, the overlapping low-Z bands can leave a gap. When one cap’s inductance resonates with another’s capacitance, and with milliohm ESR, the resulting spikes can hurt EMC or even circuit stability.

How to Reduce Multiple Capacitor Problems:

These impedance peak factors can be reduced by applying damping. Without some resistance, the resonant peaks can be very high-Q. In practice, the ESR of each capacitor (and any series resistor) determines the Q-factor of each RLC branch. A higher ESR broadens the impedance curve and lowers the peak, at the cost of raising the entire floor. In this way sometimes a series resistance with the capacitor acts well to damp the effect of peaks caused at resonance. For example, placing 0.1–1 Ω in series with a large capacitor raises its minimum impedance (from, say, 0.05 Ω to ~0.5 Ω) and spreads out the resonance bump. In simulations, a 10 µF cap with very low ESR might dip sharply to ~0.05 Ω at f₀, whereas with an added 0.5 Ω it no longer dips nearly as far (eliminating the “well”)

Effective decoupling strategies:

Use a stack of capacitors (e.g., 10–100 µF + 1–10 µF + 0.01–0.1 µF) to cover the full frequency range. As a rule of thumb, low-frequency noise is handled by caps in the 1–100 µF range, and high-frequency noise by 0.01–0.1 µF caps. A typical MCU power pin might have one 10 µF (or 4.7 µF) cap in parallel with four or more 0.1 µF ceramics, giving low impedance from a few kHz up into the hundreds of MHz. Keep in mind, place the bulk capacitor at the power input, and smaller ones with the IC for local reservoirs. Designers aim for each cap’s self-resonant notches to overlap, creating a broad well of low |Z| across the device’s transient spectrum.

Example 1: The First one shows the frequency response of a single-valued capacitor, and the second one is the damped response, where the damping is done to flatten the resonant peaks.

Example 2: As shown below, the three different value capacitors ( 1μF, 0.1μF, and 0.01 μF) give the 3 resonant and 2 antiresonant peaks. And to flatten the response series, resistance is added, which is used to cover a high-frequency spectrum.

Example 3: Here we have 10uf and 0.1uf capacitors, and look how a series resistance flattens the peaks.

Conclusion:

In summary, good decoupling means covering the device's frequency range with low impedance. We have discussed a combination of caps of various sizes placed with a short and tight layout. This will yield multiple overlapping resonance valleys on the impedance graph. Adding resistive damping or ferrites as needed will smooth out the peaks, which is the topic for another day. Overall, we have a goal of getting a flat profile and low PDN impedance. By analyzing the frequency response and applying the strategies above, one can ensure effective decoupling.