Understanding Digital Circuit Timing: Setup Time, Hold Time, Contamination Delay & Clock Skew

It is the second article in the series on propagation delay in digital circuits. There are two main things we have to make sure of when designing a digital circuit: the first is functionality, and the second is timing. we have covered the basic blocks in one article. Because time is nothing but the clock ticks when it comes to electronics. Because everything is based on these clock ticks, it determines the operating frequency, speed, and much more in an electronics circuit. We have seen circuits previously that only work in synchronisation with the clock, known as sequential circuits. When working with a microcontroller, FPGA or ASIC, the timing constraints must be met in order to achieve the correct functioning of the circuit. Today, we will see what type of timing constraints there are that we have to look into. This guide covers the fundamentals: setup time, hold time, contamination (min) delay, and clock skew, and shows how they interact in timing equations and real designs.

Timing parameters in Digital Design

Two delay metrics are important for combinational blocks:

• Tpd (Propagation Delay, max): It is the longest possible delay caused by combinational circuit elements, and it is used in setup checks.
• Tcd (Contamination Delay, min): It is the shortest possible delay, used in hold checks.
• Clock period (Tclk): The time between consecutive clock edges used for a path.

Propagation Delay vs Contamination Delay

• Propagation Delay (Tpd, max): It is the worst-case (longest) delay through a gate/logic block. Used for setup checks because we need to ensure the latest data still meets setup.

• Contamination/Min Delay (Tcd/min): It is the best-case (shortest) delay through a gate/logic block. Used for hold checks because we need to account for the earliest that a changed signal can appear at the capture flop.

Clock Skew

The time difference in clock arrival between the source flop and the destination flop. It can be caused by the long system wires from the clock to flop A and B. There will be a mismatch in the timing because signals can not arrive at the same time on all flops. The main sources of skew are clock tree imbalance, routing differences, buffers, synthesis/CTS choices, local clock gating, and PLL/BUF insertion jitter.

• Positive Skew: Capture clock arrives later than the other logic block.
• Negative Skew: Capture clock arrives earlier in comparison to the other logic block.

Intentionally, the skew is introduced to improve timing (commonly to relax setup on a critical path) while ensuring hold constraints remain satisfied.

Setup Time

Setup time (Tsu) is the minimum interval before the active clock edge during which the input data to a flip-flop must be stable. If the data is not stable before that clock edge in the specified interval, there will be setup time violations. If data arrives too late, the capture flop may sample the wrong value.

Timing check: The setup time is violated mostly by the inappropriate propagation delays. If the propagation delay from the first flop is more than the next clock edge there will be no capture of data, and data will appear after the clock or maybe at the same time, which can push the flop into metastability.

Hold Time

Hold time (Thold) is the minimum interval after the active clock edge during which the input data must remain stable. If data changes too quickly after the launch edge and arrives at the capture flop before its internal sampling latch has finished holding, the capture flop can sample a corrupted value.

Timing check: The earliest possible arrival of new data is given by Tcq + Tcd. That must not reach the capture flop before the capture flop has completed its hold interval.

Timing Paths in a Digital Circuit

A typical synchronous timing path is given below. We will examine  each and every part one by one:

Launch Edge (Flip-Flop A) → Tcq (clock-to-Q) → Combinational Logic → Tpd/Tcd (propagation/contamination) → Capture Flip-Flop B → Setup/Hold Checks

• Launch event: Flip‑flop A produces a new data value after its clock event. Now, the output of this flip-flop is fixed to that particular value. That data propagates through combinational logic.
  
• Capture event: The data is the output line of flip-flop A, which serves as the input to Flip‑flop B. It will sample the data at the next relevant clock edge.

Launch and capture are the first and last events in the timing path, but in between, a lot of things are going on, which are discussed in the next section.

Timing Equations

Setup:

Hold:

Where Jclk is clock jitter (add positive jitter conservatively to the setup equation and subtract or add appropriately to hold as a safety margin. Jitter is treated as a reduction of available timing margin.

Worked Numerical Example (Single-Cycle Path)

Given (typical numbers):

• Tclk = 5.0 ns (target period)
• Tskew = +0.10 ns (capture clock arrives 0.1 ns later)
• Tcx (Tcq) = 0.12 ns (clock-to-Q)
• Tpd = 2.80 ns (max combinational propagation)
• Tsu = 0.08 ns (setup time)
• Tcd = 0.02 ns (contamination/min delay)
• Thold = 0.05 ns (flip-flop hold requirement)
  

Setup Check:

Required period: Tcq + Tpd + Tsu - Tskew = 0.12 + 2.80 + 0.08 - 0.10 = 2.90 ns

Slack_setup = Tclk - 2.90 = 5.00 - 2.90 = 2.10 ns → PASS (comfortable margin).

Hold Check:

Allowable hold = Tcq + Tcd - Tskew = 0.12 + 0.02 - 0.10 = 0.04 ns

Slack_hold = 0.04 - Thold = 0.04 - 0.05 = -0.01 ns → HOLD VIOLATION by 10 ps.

The path meets setup easily (large slack), but a very fast path causes a hold violation. This is common in real designs: setup is comfortable while hold fails.

Common Causes of Violations and Practical Fixes

Setup Violations (typical fixes):

• Path too long: To fix this issue, try to insert a pipeline/register, reduce logic depth, or restructure the algorithm.
  
• Slow process corner: To improve, try to consider faster library cells (higher drive strength), increase VDD, and improve routing to reduce Tpd.

Hold Violations (typical fixes):

• Path too fast: we have to add a deliberate delay (place buffer/inverter), use minimum delay insertion in place-and-route, or route the path longer.
  
• Multi-cycle path: Convert the specific path to a multi-cycle if functionally allowed (Safely mark multi-cycle paths in the STA tool).

Design Tricks (Useful Skew, Multi-Cycle Paths, Retiming)

• Useful Skew: In this, the skew is deliberately introduced to relax the setup on a critical path, while ensuring the hold remains safe. This is an advanced technique used after careful analysis.
  
• Multi-Cycle Paths: If a path is architecturally allowed to take multiple cycles, mark it as multi-cycle in STA (static timing analysis). We have to set appropriate constraints instead of forcing single-cycle timing.

Conclusion

In this article, we have seen setup time and hold time in more detail with examples. The contamination delay and clock skew are interlinked with the timing equations. Setup is governed by worst-case (max) delays, while hold is governed by best-case (min) delays. Some design tricks with common violations and solutions to them are also shared in this. When it comes to the digital circuit, not only the functionality but also the timing is equally important. The series will continue for some more digital design and timing-related concepts in the future. Visit the JLCPCB section to grab this knowledge quickly.